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? 2011 semtech corporation power management 1 SC197 3.5mhz, 500ma synchronous dual step-down dc-dc regulator features input voltage 2.9v to 5.5v output voltage 0.8v to 3.3v output current capability 500ma per regulator efciency up to 94% programmable output voltages 15 high light-load efciency via automatic psave mode fast transient response oscillator frequency 3.5mhz 100% duty cycle capability quiescent current 38a typical per regulator shutdown current 0.1a typical per regulator internal soft-start over-voltage protection current limit and short circuit protection over-temperature protection under-voltage lockout floating control pin protection mlpq-ut18 2.0 x 3.0 x 0.6 (mm) package lead-free, halogen-free, and rohs/weee compliant applications smart phones and cellular phones mp3/personal media players personal navigation devices digital cameras single li-ion cell or 3 nimh/nicd cell devices devices with 3.3v or 5v internal power rails ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC197 contains two identical high efciency 500ma step-down regulators designed for use in battery- powered applications. each regulator includes 15 programmable output voltage settings that can be selected using the four control pins, eliminating the need for external feedback resistors. the output voltage can be fxed to a single setting or dynamically switched between diferent levels. pulling all four control pins low disables the output. the SC197 operates at a fxed 3.5mhz switching frequency in normal pwm (pulse-width modulation) mode. a vari - able frequency psave (power save) mode is used to optimize efciency at light loads for each output setting. built-in hysteresis prevents chattering between the two modes. the SC197 provides several protection features to safe - guard the device under stressed conditions. these include short circuit protection, over-temperature protection, under-voltage lockout, and soft-start to control in-rush current. these features, coupled with the small 2.0 x 3.0 x 0.6 (mm) package make the SC197 a versatile device ideal for step-down regulation in products needing high ef - ciency and a small pcb footprint. sc 197 ina ctl 3 a ctl 2 a ctl 1 a ctl 0 a lxa outa gnda v outa 0 . 8 v to 3 . 3 v v in 2 . 9 v to 5 . 5 v l xa 1 . 0 h c out a 10 f c in a 4 . 7 f control logic for output a inb ctl 3 b ctl 2 b ctl 1 b ctl 0 b lxb outb gndb v outb 0 . 8 v to 3 . 3 v v in 2 . 9 v to 5 . 5 v l xb 1 . 0 h c out b 10 f c in b 4 . 7 f control logic for output b typical application circuit january 17, 2011
SC197 2 pin confguration marking information ordering information device package SC197ultrt (1)(2) mlpq-ut18 2 x 3 SC197evb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) lead-free packaging only. device is weee and rohs compliant and halogen-free. top view ctl 1 a 16 17 18 14 13 12 11 10 5 4 3 2 1 7 8 9 6 15 ctl 0 a outb gndb lxb nc nc lxa gnda outa ctl 0 b ctl 1 b c t l 2 a c t l 3 a i n a c t l 2 b c t l 3 b i n b 197 yw xxx mlpq-ut18;f2fxf3,f18flead ja f=f77c/w tablef1fCfoutputfvoltagefsettings ctl3a/b ctl2a/b ctl1a/b ctl0a/b v outa/b 0 0 0 0 shutdown 0 0 0 1 0.80 0 0 1 0 1.00 0 0 1 1 1.20 0 1 0 0 1.40 0 1 0 1 1.50 0 1 1 0 1.60 0 1 1 1 1.80 1 0 0 0 1.85 1 0 0 1 1.90 1 0 1 0 2.00 1 0 1 1 2.20 1 1 0 0 2.50 1 1 0 1 2.80 1 1 1 0 3.00 1 1 1 1 3.30 197f=fSC197 ywf=fdatefcode xxxf=flotfnumber
SC197 3 exceeding the above specifcations may result in permanent damage to the device or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114. (2) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb per jesd51 standards. absolute maximum ratings ina, inb (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 lxa, lxb voltage (v) . . . . . . . . . . . . . . . . . . . . . -1.0 to (v in +0.5) other pins (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v in + 0.3) output short circuit to gnd . . . . . . . . . . . . . . . . continuous esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 recommended operating conditions ambient temperature range (c) . . . . . . . . . . . -40 t a +85 input voltage (v) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 v in 5.5 thermal information thermal resistance, junction to ambient (2) (c/w) . . . . 7 7 storage temperature range (c) . . . . . . . . . . . . -65 to +150 peak ir reflow temperature (10s to 30s) (c) . . . . . . . +260 unless otherwise specifed: v in = 3.6v, c in = 4.7f, c out =10f, l x =1h, v out =1.8v, t j(max) =125c, t a = -40 to +85 c. typical values are t a =+25 c. all specifcations are identical for converters a and b. parameter symbol (1) condition min typ max units output voltage range v out 0.8 3.3 (2) v output voltage tolerance v out_tol i out = 200ma -2.0 2.0 % psave mode 1.5 line regulation v linereg 2.9 v in 5.5v, i out = 200ma 0.3 %/v load regulation v loadreg 200ma i out 500ma -0.4 % output current capability i out 500 ma current limit threshold i limit 800 1300 ma foldback current limit i fb_lim i load > i limit 150 ma under-voltage lockout v uvlo rising v in 2.9 v hysteresis 200 mv quiescent current i q no switching, i out = 0ma 38 60 a shutdown current i sd v ctl 0-3 = 0v 0.1 1.0 a lx leakage current i lx into lx pin 0.1 1.0 a high side switch resistance (3) r dson_p i out = 100ma 250 m low side switch resistance (4) r dson_n i out = 100ma 350 electrical characteristics
SC197 4 parameter symbol (1) condition min typ max units switching frequency f sw 2.8 3.5 4.2 mhz soft-start t ss v out = 90% of fnal value 100 500 s thermal shutdown t ot rising temperature 160 c thermal shutdown hysteresis t hyst 20 c logic inputs - ctl0a, ctl1a, ctl2a, ctl3a, ctl0b, ctl1b, ctl2b, and ctl3b input high voltage v ih 1.2 v input low voltage v il 0.4 v input high current i ih v ctl 0-3 = v in -2.0 5.0 a input low current i il v ctl 0-3 = gnd -2.0 2.0 a notes (1) all symbol references apply equally to a and b devices. (2) maximum output voltage is limited to vin if the input is less than 3.3v. (3) measured from ina to lxa or from inb to lxb. (4) measured from lxa to gnda or from lxb to gndb. electrical characteristics (continued)
SC197 5 typical characteristics efciencyfvs.fi out f(t a f=f-40c) 0 10 20 30 40 50 60 70 80 90 100 0 . 1 1 10 100 1000 load current ( ma ) e f f i c i e n c y ( % ) 3 . 3 v 2 . 8 v 1 . 8 v 0 . 8 v efciencyfvs.fi out f(t a f=f25c) 0 10 20 30 40 50 60 70 80 90 100 0 . 1 1 10 100 1000 load current ( ma ) e f f i c i e n c y ( % ) 3 . 3 v 2 . 8 v 1 . 8 v 0 . 8 v efciencyfvs.fi out f(t a f=f85c) 0 10 20 30 40 50 60 70 80 90 100 0 . 1 1 10 100 1000 load current ( ma ) e f f i c i e n c y ( % ) 3 . 3 v 2 . 8 v 1 . 8 v 0 . 8 v 4 . 2 v 5 . 0 v 70 75 80 85 90 95 100 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 v out ( v ) e f f i c i e n c y ( % ) 3 . 6 v 70 75 80 85 90 95 100 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 v out ( v ) e f f i c i e n c y ( % ) 3 . 6 v 4 . 2 v 5 . 0 v 70 75 80 85 90 95 100 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 v out ( v ) e f f i c i e n c y ( % ) 3 . 6 v 4 . 2 v 5 . 0 v v in = 4.0v for v out = 3.3v, v in = 3.6v for all others. c in = 4.7f, c out = 10f, l x = 1h, t a = 25c unless otherwise noted. efciencyfvs.fv out f(t a f=f-40c) efciencyfvs.fv out f(t a f=f25c) efciencyfvs.fv out f(t a f=f85c) i out = 300ma i out = 300ma i out = 300ma
SC197 6 v in = 4.0v for v out = 3.3v, v in = 3.6v for all others. c in = 4.7f, c out = 10f, l x = 1h, t a = 25c unless otherwise noted. frequencyfvs.ftemperature 3 . 0 3 . 2 3 . 4 3 . 6 3 . 8 4 . 0 - 50 - 30 - 10 10 30 50 70 90 temperature ( c ) f r e q u e n c y ( m h z ) 0 . 8 v 3 . 3 v 1 . 8 v 2 . 8 v loadfregulationf(v out f=f1.8v) 25 c 1 . 76 1 . 78 1 . 80 1 . 82 1 . 84 1 . 86 0 100 200 300 400 500 load current ( ma ) o u t p u t v o l t a g e ( v ) 85 c - 40 c - 40 c 85 c 25 c 1 . 76 1 . 78 1 . 80 1 . 82 1 . 84 1 . 86 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 v in ( v ) v o u t ( v ) linefregulationf(v outf =1.8v) 81 82 83 84 85 86 87 88 89 90 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 v in ( v ) e f f i c i e n c y ( % ) - 40 c 25 c 85 c efciencyfvs.fv in f(v outf =1.8v) typical characteristics (continued) i out = 300ma i out = 200ma v in = 3.6v i out = 200ma
SC197 7 typical characteristics (continued) lightfloadfswitchingffv out f=f1.8v time (400n s/div) s/div) /div) v lx (2v/div) v out (50mv/div) i lx (200ma/div) lightfloadfswitchingffv out f=f1.0v time (400n s/div) s/div) /div) v lx (2v/div) v out (50mv/div) i lx (200ma/div) lightfloadfswitchingffv out f=f2.8v time (400n s/div) s/div) /div) v lx (2v/div) i out = 10ma v out (50mv/div) i lx (200ma/div) lightfloadfswitchingffv out f=f3.3v time (400n s/div) s/div) /div) v lx (2v/div) v out (50mv/div) i lx (200ma/div) heavyfloadfswitchingffv out f=f1.0v time (200n s/div) s/div) /div) i lx (500ma/div) v out (50mv/div) v lx (2.0v/div) heavyfloadfswitchingffv out f=f1.8v time (200n s/div) s/div) /div) i lx (500ma/div) v out (50mv/div) v lx (2v/div) i out = 10ma 0ma 0ma 0ma i out = 500ma i out = 10ma i out = 10ma i out = 500ma 0ma 0ma 0ma
SC197 8 typical characteristics (continued) heavyfloadfswitchingffv out f=f2.8v time (200n s/div) s/div) /div) i lx (200ma/div) v out (50mv/div) v lx (2v/div) heavyfloadfswitchingffv out f=f3.3v time (200n s/div) s/div) /div) i lx (500ma/div) v out (50mv/div) v lx (2v/div) heavyfloadfsoft-start time (40 s/div) s/div) /div) v out (1.0v/div) i out (500ma/div) i lx (500ma/div) lightfloadfsoft-start time (40 s/div) s/div) /div) v out (1.0v/div) i out (10ma/div) i lx (500ma/div) loadftransientfresponseff10ftof100ma time (20 s/div) s/div) /div) i lx (500ma/div) v out (100mv/div) i load (50ma/div) loadftransientfresponseff10ftof500ma time (20 s/div) s/div) /div) i lx (500ma/div) v out (100mv/div) i load (500ma/div) i out = 10ma i out = 500ma 0ma 0ma i out = 500ma i out = 500ma, v out = 1.8v 0ma v ctl2-0 (5v/div) 0ma 0ma v ctl2-0 (5v/div)
SC197 9 typical characteristics (continued) loadftransientfresponseff200ftof500ma time (20 s/div) s/div) /div) i lx (500ma/div) v out (100mv/div) i load (500ma/div) lineftransientfresponseffpwm time (40 s/div) s/div) /div) i lx (200ma/div) v out (100mv/div) v in 500mv/div) vidftransientfresponseffpwm time (20 s/div) s/div) /div) v ctl2 (5.0v/div) v out (500mv/div) i lx (200ma/div) v out = 1.2v to 1.8v transition, i out = 500ma vidftransientfresponseffpsave time (100 s/div) s/div) /div) v ctl2-0 (5.0v/div) v out (500mv/div) i lx (200ma/div) v out = 1.2v to 1.8v transition, r load = 120 lineftransientfresponseffpsave time (40 s/div) s/div) /div) i lx (200ma/div) v out (100mv/div) v in (500mv/div) shutdownftransientfresponsef time (20 s/div) s/div) /div) i lx (200ma/div) v out (1v/div) v ctl3-0 (5v/div) v in = 3.5 to 4.0v, v out = 1.8v, i out = 400ma v out = 1.8v v out = 1.8v, i out = 500ma v in = 3.5 to 4.0v, v out = 1.8v, i out = 10ma 4.0v 3.5
SC197 10 pin descriptions pin pin name pin function 1 ctl 1a control bit 1a see table 1, page 2, for output voltage selection. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl1 is pulled above the logic high threshold. 2 ctl 0a control bit 0a see table 1, page 2, for output voltage selection. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl0 is pulled above the logic high threshold. 3 out b output voltage sense b output voltage regulation point (connection node of inductor and output capacitor). 4 gndb ground b reference and power ground for the SC197. 5 lx b switching output b connect an inductor between this pin and the load to flter the pulsed output current. 6 nc no connection 7 in b input power supply b connect a bypass capacitor from this pin to gnd. 8 ctl 3b control bit 3b see table 1, page 2, for output voltage selection. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl3 is pulled above the logic high threshold. 9 ctl 2b control bit 2b see table 1, page 2, for output voltage selection. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl2 is pulled above the logic high threshold. 10 ctl 1b control bit 1b see table 1, page 2, for output voltage selection. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl1 is pulled above the logic high threshold. 11 ctl 0b control bit 0b see table 1, page 2, for output voltage selection. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl0 is pulled above the logic high threshold. 12 out a output voltage sense a output voltage regulation point (connection node of inductor and output capacitor). 13 gnda ground a reference and power ground for the SC197. 14 lx a switching output a connect an inductor between this pin and the load to flter the pulsed output current. 15 nc no connection 16 in a input power supply a connect a bypass capacitor from this pin to gnd. 17 ctl 3a control bit 3a see table 1, page 2, for output voltage selection. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl3 is pulled above the logic high threshold. 18 ctl 2a control bit 2a see table 1, page 2, for output voltage selection. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl2 is pulled above the logic high threshold. notes (1) any of pins ctl3a, ctl2a, ctl1a, and ctl0a may be connected together to function as a single input for enable and disable. (2) any of pins ctl3b, ctl2b, ctl1b, and ctl0b may be connected together to function as a single input for enable and disable. (3) a and b devices are electrically isolated and share no common connections internally. ctlxa and ctlxb pins may only be connected together when a and b devices share the same power source, ina and inb are connected together, and gnda and gndb are connected together. note that connecting any ctlxa and ctlxb pins together will force both a and b devices to make output voltage changes simultaneously.
SC197 11 block diagram control logic p limit amp current amp n limit amp osc & slope generator pwm comp error amp 500 mv ref ctl 2 b ctl 1 b ctl 0 b out b ctl 3 b gnd b lx b in b voltage select 4 5 7 11 3 10 9 8 psave comp control logic p limit amp current amp n limit amp osc & slope generator pwm comp error amp 500 mv ref ctl 2 a ctl 1 a ctl 0 a out a ctl 3 a gnd a lx a in a voltage select 13 14 16 2 12 1 18 17 psave comp
SC197 12 general description the SC197 contains two identical synchronous step-down pwm (pulse width modulated) dc-dc regulators. each regulator utilizes a 3.5mhz fxed-frequency voltage mode architecture. each is designed to operate in fixed-fre - quency pwm mode and enter psave (power save) mode utilizing pulse frequency modulation under light load conditions to maximize efciency. each regulator requires only two capacitors and a single inductor to be imple - mented in most systems. the switching frequency has been chosen to minimize the size of the inductor and capacitors while maintaining high efficiency. output voltage is programmable, eliminating the need for exter - nal programming resistors. loop compensation is also internal, eliminating the need for external components to control stability. programmable output voltage the SC197 has 15 fxed output voltage levels which can be individually selected by programming the ctlx(a/b) control pins (see table 1 on page 2 for settings). control pins with an a sufx refer to the a output, and the b sufx refers to the b output. a and b devices are electri - cally isolated and share no connections internal to the package. the a or b device is disabled whenever all four ctlxa or all four ctlxb pins are pulled low. the a or b device is enabled whenever at least one of the ctlxa or ctlxb pins is pulled high. this confguration eliminates the need for a dedicated enable pin. each ctlx(a/b) pin is internally pulled down via 1m if v in is below 1.5v or if the voltage on the control pin is below the input high voltage. this ensures that the output is disabled when power is applied if there are no inputs to the ctlx(a/b) pins. each weak pull-down is disabled whenever its pin is pulled high and remains disabled until all ctlx(a/b) pins are pulled low. the output voltage can be set using diferent methods. if a static output voltage is required, the ctlx(a/b) pins can be tied to either in or gnd to set the desired voltage whenever power is applied at in. if enable control is required, each ctlx(a/b) pin can be tied to either gnd or to a microprocessor i/o line to create the desired control code whenever the control signal is forced high. this approach is equivalent to using the ctlx(a/b) pins collec - tively as a single enable pin. a third option is to connect each of the four ctlx(a/b) pins to individual micropro - cessor i/o lines. any of the 15 output voltages can be programmed using this approach. if only two output voltages are needed, the ctlx(a/b) pins can be combined in a way that will reduce the number of i/o lines to 1, 2, or 3, depending on the control code for each desired voltage. other ctlx(a/b) pins could be hard wired to gnd or in. this option allows dynamic voltage adjust - ment for systems that reduce the supply voltage when entering sleep states. note that applying all zeros to the ctlx(a/b) pins when changing the output voltages will temporarily disable the device, so it is important to avoid this combination when dynamically changing levels. ctlxa and ctlxb pins may only be connected together when a and b devices share the same power source; i.e., ina and inb pins are connected together, and gnda and gndb are connected together. note that connecting any ctlxa and ctlxb pins together will force both a and b d e v i c e s t o m a k e o u t p u t v o l t a g e c h a n g e s simultaneously. adjustable output voltage selection if an output voltage other than one of the 15 program - mable settings is needed, an external resistor divider network can be added to the SC197 to adjust the output voltage setting. this network scales the output based on the resistor ratio and the programmed output setting. the resistor values can be determined using the equa - tion. note that v out may refer to either the a or b device. 1 fb leak 2 fb 2 fb 1 fb set out r i r r r v v u ? ? o ? ? a u where v out is the desired output voltage, v set is the voltage setting selected by the ctlx(a/b) pins, r fb1 is the resistor between the output capacitor and the out(a/b) pin, r fb2 is the resistor between the out(a/b) pin and ground, and i leak is the leakage current into the out(a/b) pin during normal operation. the current into the out(a/b) pin is typically 1a, so the last term of the equa - tion can be neglected if the current through r fb2 is much larger than 1a. selecting a resistor value of 10k or applications information
SC197 13 lower will simplify the design. if i leak is neglected and r fb2 is fxed, r fb1 can be determined using the equation. set set out 2 fb 1 fb v v v r r u inserting resistance in the feedback loop will adversely afect the systems transient performance if feed-forward capacitance is not included in the circuit. the circuit in figure 1 illustrates how the resistor divider and feed- forward capacitor can be added to the SC197 schematic. the value of feed-forward capacitance needed can be determined using the equation. 5 . 0 v v v r 5 . 0 v v 10 4 c set set out 1 fb 2 out set 6 ff u u sc 197 ina ctl 3 a ctl 2 a ctl 1 a ctl 0 a lxa outa gnda v out v in l x c out c in enable c ff r fb 1 r fb 2 figuref1ffapplicationfcircuitfwithfexternalfresistors to simplify the design, it is recommended to program the output setting to 1.0v, use resistor values smaller than 10k, and include a feed-forward capacitance calculated with the equation above. if the output voltage is set to 1.0v, the previous equation reduces to the following. 1 v r 5 . 0 v 10 8 c out 1 fb 2 out 6 ff u u example: an output voltage of 1.3v is desired, but this is not a pro - grammable option. what external component values for figure 1 are needed? solution: to keep the circuit simple, set r fb2 to 10k so current into the out(a/b) pin can be neglected and set the ctl3-0 pins to 0010 (1.0v setting). the necessary component values are as follows: : u k 3 v v v r r set set out 2 fb 1 fb nf 69 . 5 1 v r 5 . 0 v 10 8 c out 1 fb 2 out 6 ff u u pwm operation normal pwm operation occurs when the output load current exceeds the psave threshold. in this mode, the pmos high side switch is activated with the duty cycle required to produce the output voltage programmed by the ctlx(a/b) pins. an internal synchronous nmos recti - fer eliminates the need for an external schottky diode on the lx(a/b) pin. the duty cycle (percentage of time pmos is active) increases as v in decreases to maintain output voltage regulation. as the input voltage approaches the programmed output voltage, the duty cycle approaches 100% (pmos always on) and the device enters a pass- through mode. this mode remains active until the input voltage increases or the load decreases enough to allow pwm switching to resume. power save mode operation when the load current decreases below the psave threshold, pwm switching stops and the device auto - matically enters psave mode. this threshold varies depending on the input voltage and output voltage setting, optimizing efciency for all possible load currents in pwm or psave mode. while in psave mode, output voltage regulation is controlled by a series of switching bursts. during a burst, the inductor current is limited to a peak value which controls the on-time of the pmos switch. after reaching this peak, the pmos switch is dis - abled and the inductor current decreases to near 0ma. switching bursts continue until the output voltage climbs to v out +2.5% or until the psave current limit is reached. switching is then stopped to eliminate switching losses, enhancing overall efciency. switching resumes when the output voltage reaches the lower threshold of v out and continues until the upper threshold again is reached. note that the output voltage is regulated hysteretically while in psave mode between v out and v out + 2.5%. the applications information (continued)
SC197 14 period and duty cycle while in psave mode are solely determined by v in and v out until pwm mode resumes. this can result in the switching frequency being much lower than the pwm mode frequency. if the output load current increases enough to cause v out to decrease below the psave exit threshold (v out -2%), the device automatically exits psave and operates in continu - ous pwm mode. note that the psave high and low threshold levels are both set at or above v out to minimize undershoot when the SC197 exits psave. figure 2 illus - trates the transitions from pwm mode to psave mode and back to pwm mode. v out - 2 % v out v out + 2 . 5 % load demand ( i out ) burst off v lx time pwm mode at medium / high load psave mode at light load pwm mode at medium / high load psave exit figuref2fftransitionsfbetweenfpwmfandfpsavefmodes protectionffeatures the SC197 provides the following protection features: soft-start operation over-voltage protection current limit thermal shutdown under-voltage lockout soft-start the soft-start sequence is activated after a transition from an all zeros ctlx(a/b) code to a non-zero ctlx(a/b) code enables the device. at start-up, the pmos current limit is stepped through four levels: 25%, 40%, 60%, and 100%. each step is maintained for 60s following an internal ref - erence start up of 20s, resulting in a total nominal ? ? ? ? ? applications information (continued) start-up period of 260s. if v out reaches 90% of the target within the first 2 steps, the device continues in psave mode at the end of soft-start; otherwise, it goes into pwm mode. note the v out ripple in psave mode can be larger than the ripple in pwm mode. over-voltage protection ovp (over-voltage protection) ensures the output voltage does not rise to a level that could damage its load. when v out exceeds the regulation voltage by 15%, the pwm drive is disabled. switching does not resume until v out has fallen below the regulation voltage by 2%. current limit the SC197 switching stage is protected by a current limit function. if the output load exceeds the pmos current limit for 32 consecutive switching cycles, the device enters fold-back current limit mode and the output current is limited to approximately 150ma. under these conditions, the output voltage will be the product of i fb-lim and the load resistance. the load must fall below i fb-lim for the device to exit fold-back current limit mode. this function makes the device capable of sustaining an indefnite short circuit on its output under fault conditions. thermal shutdown the SC197 has a thermal shutdown feature to protect the device if the junction temperature exceeds 160c. during thermal shutdown, the pmos and nmos switches are both disabled, tri-stating the lx(a/b) output. when the junction temperature drops by the hysteresis value (20c), the device goes through the soft-start process and resumes normal operation. under-voltage lockout uvlo (under-voltage lockout) activates when the supply voltage drops below the uvlo threshold. this prevents the device from entering an ambiguous state in which regulation cannot be maintained. hysteresis of approxi - mately 200mv is included to prevent chattering near the threshold. inductor selection the SC197 is designed to operate with a 1h inductor between the lx(a/b) pin and the out(a/b) pin. other values may lead to instability, malfunction, or out-of- specifcation performance. the specifed current levels
SC197 15 for psave entry, psave exit, and current limit are depen - dent on the inductor value. the SC197 converter has internal loop compensation. the compensation is designed to work with a specifc single- pole output filter corner frequency defined by the equation. 28 7 & & / i u s where l = 1h and c out = 10f. when selecting output flter components, the lc product should not vary over a wide range. selection of smaller inductor and capacitor values will move the corner fre - quency, potentially impacting system stability. it is also important to consider the change in inductance with dc bias current when choosing an inductor. the inductor saturation current is specifed as the current at which the inductance drops a specifc percentage from the nominal value (approximately 30%). except for short- circuit or other fault conditions, the peak current must always be less than the saturation current specifed by the manufacturer. the peak current is the maximum load current plus one half of the inductor ripple current at the maximum input voltage. load and/or line transients can cause the peak current to exceed this level for short dura - tions. maintaining the peak current below the inductor saturation specifcation keeps the inductor ripple current and the output voltage ripple at acceptable levels. manufacturers often provide graphs of actual inductance and saturation characteristics versus applied inductor current. the saturation characteristics of the inductor can vary significantly with core temperature. core and ambient temperatures should be considered when exam - ining the core saturation characteristics. when the inductor value has been determined, the dc resistance (dcr) must be examined. efficiency can be optimized by lowering the inductors dcr as much as pos - sible. low dcr in an inductor requires either more surface area for the increased wire diameter or fewer turns to reduce the length of the copper winding. fewer turns requires an inductor core with a larger cross-sectional area applications information (continued) manufacturer/part no. l (h) dcr max (?) rated current (a) l at rated current (h) dimensions lxwxh (mm) murata lqm2hpn1r0 120% 0.13 1.5 0.78 2.5x2.0x1.2 murata lqh3npn1r0 120% 0.07 1.7 0.78 3.0x3.0x1.5 coilcraft lpo4815 120% 0.036 1.9 0.8 4.8x4.8x1.5 coilcraft lps3010 120% 0.085 1.6 0.7 3.0x3.0x1.0 shielded fdk mipwt3226d1r5 1.530% 0.09 1.2 0.9 3.2x2.6x0.8 fdk mipf2520d1r5 1.530% 0.07 1.5 0.9 3.2x2.6x0.8 tayo yuden ckp32161r5m 1.520% 0.13 1 0.5 3.2x1.6x0.8 in order to maintain the same saturation characteristics. the inductor size must always be considered when exam - ining the inductor dcr to determine the best compromise between dcr and component area on a pcb. note that the ripple component of the inductor is a small percent - age of the dc load. ac losses in the inductor core and winding do not contribute significantly to the total losses. magnetic felds associated with the output inductor can interfere with nearby circuitry. this can be minimized by the use of low-noise shielded inductors which use the minimum gap possible to limit the distance that magnetic felds can radiate from the inductor. shielded inductors, however, typically have a higher dcr and are, therefore, less efcient than a similar sized non-shielded inductor. final inductor selection depends on various design con - siderations such as efciency, emi, size, and cost. table 2 lists the manufacturers of recommended inductor options. the inductors with larger packages tend to provide better overall efficiency, while the smaller package inductors provide decent efciency with reduced footprint or height. the saturation current ratings and dc characteristics are also shown. table 2 recommended inductors manufacturer part number l (h) dcr (?) saturation current (ma) l at 400ma (h) dimensions lxwxh (mm) murata lqm21pn1r0mc0 1.020% 0.19 800 0.75 2.0x1.25x0.55 murata lqm2hpn1r0mj0 1.020% 0.09 1500 0.95 2.5x2.0x1.1 murata lqm31pn1r0m00 1.020% 0.12 1200 0.95 3.2x1.6x0.85 taiyo yuden ckp25201r0m-t 1.020% 0.08 800 0.88 2.5x2.0x1.0 toko mdt2012-cr1r0n 1.030% 0.08 1350 1.00 2.0x1.25x1.0 fdk mipsz2012d1r0 1.030% 0.09 1100 1.00 2.0x1.25x1.0 fdk mipsu2520d1r0 1.030% 0.08 1300 0.78 2.5x2.0x0.5 fdk mipsa2520d1r0 1.330% 0.09 1200 1.20 2.5x2.0x1.2 taiyo yuden brc1608t1r0m 1.020% 0.18 850 0.90 1.6x0.8x0.8
SC197 16 c out selection the internal voltage loop compensation in the SC197 limits the minimum output capacitor value to 10f. this is due to its infuence on the the loop crossover frequency, phase margin, and gain margin. increasing the output capacitor above this minimum value will reduce the cross - over frequency and provide greater phase margin. the output capacitor determines the output voltage ripple and contributes load current during large step load transitions. a capacitor between 10f and 22f will usually be adequate in stabilizing the output during large load transitions. capacitors with x7r or x5r ceramic dielectric are recom - mended for their low esr and superior temperature and voltage characteristics. y5v capacitors should not be used as their temperature coefcients make them unsuitable for this application. in addition to ensuring stability, the output capacitor serves other important functions. this capacitor deter - mines the output voltage ripple as capacitance increases, ripple voltage decreases. it also supplies current during a large load step for a few switching cycles until the control loop responds (typically 3 switching cycles). once the loop responds, regulation is restored and the desired output is reached. during the period prior to pwm operation resuming, the relationship between output voltage and output capacitance can be approximated using the following equation. f v i 3 c droop load out u ' u this equation can be used to approximate the minimum output capacitance needed to ensure voltage does not droop below an acceptable level. for example, a load step from 50ma to 400ma requiring droop less than 50mv would require the minimum output capacitance to be as follows. f 0 . 6 10 4 05 . 0 4 . 0 3 c 6 out p u u u applications information (continued) in this example, using a standard 10f capacitor would be adequate to keep voltage droop less than the desired limit. note that if the voltage droop limit were decreased from 50mv to 25mv, the output capacitance would need to be increased to at least 12f (twice as much capaci - tance for half the droop). capacitance will decrease from the nominal value when a ceramic capacitor is biased with a dc current, so it is important to select a capacitor whose value exceeds the necessary capacitance value at the pro - grammed output voltage. check the manufacturers capacitance vs. dc voltage graphs when selecting an output capacitor to ensure the capacitance will be adequate. table 3 lists the manufacturers of recommended output capacitor options. tablef3fffrecommendedfoutputfcapacitors manufacturer part nunber value (f) type rated voltage (vdc) dimensions lxwxh (mm) case size murata grm188r010me47d 1020% x5r 6.3 1.6x0.8x0.8 0603 murata grm21br60j106k 1010% x5r 6.3 2.0x1.25x1.25 0805 taiyo yuden jmk107bj106ma-t 1020% x5r 6.3 1.6x0.8x0.8 0603 tdk c1608x5r0j106mt 1020% x5r 6.3 1.6x0.8x0.8 0603 c in selection the SC197 input source current will appear as a dc supply current with a triangular ripple imposed on it. to prevent large input voltage ripple, a low esr ceramic capacitor is required. a minimum value of 4.7f should be used. it is important to consider the dc voltage coefcient charac - teristics when determining the actual required value. for example, a 10f, 6.3v, x5r ceramic capacitor with 5v dc applied may exhibit a capacitance as low as 4.5f. the value of required input capacitance is estimated by deter - mining the acceptable input ripple voltage and calculating the minimum value required for c in using the equation f esr i v v v 1 v v c out in out in out in ? ? 1 ? ' ? ? 1 ?
SC197 17 applications information (continued) the input voltage ripple is at maximum level when the input voltage is twice the output voltage (50% duty cycle scenario). the input capacitor provides a low impedance loop for the edges of pulsed current drawn by the pmos switch. low esr/esl x5r ceramic capacitors are recommended for this function. to minimize stray inductance, the capaci - tor should be placed as closely as possible to the in and gnd pins of the SC197. table 4 lists the recommended input capacitor options from diferent manufacturers. tablef4fffrecommendedfinputfcapacitors manufacturer part nunber value (f) type rated voltage (vdc) dimensions lxwxh (mm) case size murata grm188r0475 4.710% x5r 6.3 1.6x0.8x0.8 0603 murata grm188r60j106k 1010% x5r 6.3 1.6x0.8x0.8 0603 taiyo yuden jmk107bj475ka 4.710% x5r 6.3 1.6x0.8x0.8 0603 tdk c1608x5r0j475kt 4.710% x5r 6.3 1.6x0.8x0.8 0603 pcb layout considerations the layout diagram in figure 3 shows a recommended pcb top-layer for the SC197 and supporting components. specifed layout rules must be followed since the layout is critical for achieving the performance specified in the electrical characteristics table. poor layout can degrade the performance of the dc-dc converter and can contrib - ute to emi problems, ground bounce, and resistive voltage losses. poor regulation and instability can result. the following guidelines are recommended for designing a pcb layout: c ina and c inb should be placed as close to the in and nc pins as possible. this capacitor provides a low impedance loop for the pulsed currents present at the buck converters input. use short wide traces to minimize trace impedance. this will also minimize emi and input voltage ripple by localizing the high frequency current pulses. 1. keep the lxa and lxb pin traces as short as possible to minimize pickup of high frequency switching edges to other parts of the circuit. route a trace from the outa pin and connect it directly to the terminal of c outa . repeat by adding a trace between the outb pin and the c outb capactor. provide space between the outa trace and l xa to minimize noise and magnetic interference. also provide space between outb and l xa . c outa and c outb should have a direct return to ground with minimized trace length. use a ground plane referenced to ground pins gnda and gndb. use multiple vias to connect to ground to further reduce noise and interference on sensitive circuit nodes. minimize the resistance from the output and ground pins to the load. this will reduce errors in dc regulation due to voltage drops in the traces. l xa c outa c ina l xb c inb c out b i n b ctl 1 a 16 17 18 14 13 12 11 10 5 4 3 2 1 7 8 9 6 15 ctl 0 a outb gndb lxb nc lxa outa ctl 0 b ctl 1 b c t l 2 a c t l 3 a i n a c t l 2 b c t l 3 b gnda nc figuref3ffrecommendedfpcbflayoutf 2. 3. 4. 5. 6.
SC197 18 2.00 1.90 2.10 notes: 0.08 18 0.85 0.00 0.50 1.10 1.00 0.05 0.60 (0.152) - - 0.10 2.90 3.00 3.10 0.40 bsc 0.25 0.30 0.35 coplanarity applies to the exposed pad as well as the terminals. 2. controlling dimensions are in millimeters (angles in degrees). 1. dimensions e bbb aaa a1 a2 d1 e1 dim n l e d a millimeters max min nom seating plane b 0.15 0.20 0.25 a1 aaa c a a2 c 1.85 2.00 2.10 pin 1 indicator (laser mark) a b d e n 1 0.310 e 1.20 2.00 0.285 e 0.80 bbb c a b bxn 0.310 e 1.20 2.00 lxn e1 d1 0.285 e 0.80 0.30 x 45 chamfer outline drawing mlpq-ut18
SC197 19 land pattern mlpq-ut18 this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 2. thermal vias in the land pattern of the exposed pad shall be connected to a system ground plane. functional performance of the device. failure to do so may compromise the thermal and/or 3. controlling dimensions are in millimeters (angles in degrees). 1. dim x y k p c g millimeters (3.05) 0.20 0.65 0.40 1.00 2.40 dimensions 3.70 z z1 2.70 g1 1.40 c1 (2.05) h 2.00 0.310 p 1.20 2.00 g (c) z 0.285 p g1 (c1) z1 0.285 p 0.80 k 0.80 0.310 p 1.20 2.00 h x y
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information SC197 20 ? semtech 2011 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any conse - quence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or elec - trical stress including, but not limited to, exposure to parameters beyond the specifed maximum ratings or operation outside the specifed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life- support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners.

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